Phase detectors have been long used in the art for various applications. One primary application of the phase detection is a phase-locked loop ("PLL"). Typically, a PLL includes a phase detector, a low pass filter, and a voltage controlled oscillator ("VCO"). The phase detector compares the phase of an incoming signal with that of the VCO, and outputs a periodic signal having a duty cycle proportional to the phase difference between the incoming signal and the VCO. The output periodic signal is filtered to achieve a mean DC voltage which adjusts the frequency of the VCO to track that of the incoming signal. One common application of the PLL is a high-Q resonant filter.
FIG. 1a illustrates a timing diagram of an ideal characteristic for a phase detector having two inputs, R and V, and an output, Q. For this detector, the output signal, Q, is triggered by the rising edges of the input signals, R and V. Specifically, Q goes high on a rising edge of R and goes low on a rising edge of V. The resultant timing characteristic of Q may be filtered over time to generate a mean DC voltage. The amplitude of this DC voltage is, therefore, proportional to the phase difference between input signals R and V.
FIG. 1b illustrates a state diagram corresponding to the timing diagram of FIG. 1a. As appreciated from FIG. 1b, the state diagram has only two states, a first for Q=0 and a second for Q=1. Moreover, the sole criteria for switching between the two states are the rising edges of R and V. Thus, as R goes high, the output Q goes high regardless of whether R then goes low. Similarly, as V goes high, the output Q goes low regardless of whether V then goes low.
While the timing chart and state diagram of FIGS. 1a-1b provide optimal results in theory, they do not address an anomaly which arises once implemented in hardware. Specifically, each of the two-state changes occurs only after a finite delay caused by the circuitry implementing the phase detector. This delay is caused by the propagation delays within the various logic gates or components of the phase detector. Consequently, the more complicated the device componentry, the greater risk of delay and the greater deviation from the desired effects illustrated in FIGS. 1a and 1b.
FIG. 2 illustrates a non-linear, or "dead zone", effect known in the art of phase detectors. Particularly, FIG. 2 illustrates a graph of the DC average of a phase detector output versus the phase difference between the phase detector inputs. Ideally, the DC average output of the phase detector should be linearly proportional to the phase difference between the detector inputs. As shown in FIG. 2, however, a significant range of non-linearity is created where the phase difference of the input signals approaches zero degrees.
The non-linearity of FIG. 2 is caused by the propagation delays imposed by the phase detection circuitry. Specifically, the absolute delay of the individual gates, the gate-to-gate variation in delays, and the transition dependence of the delay all contribute to the non-linearity. The non-linearity causes jitter in the detector output, and limits its operating frequency range. Ironically, most PLLs are implemented to operate in the middle of the DC output range of the phase detector (e.g., where the phase difference between the input signal and the VCO output approaches zero). Thus, these PLLs operate in precisely the area of the dead zone. Consequently, the non-linear response is most problematic for many typical operations of the PLL. Moreover, the dead zone is not repeatable and, hence, not predictable; nor is it commonly characterized on a phase detector data sheet. Instead, it is at best a probabilistic function which varies with at least temperature, time and operating environment.
Various remedies have been attempted to reduce the problems created by the dead zone. One known approach is moving the dead zone by injecting a controlled amount of DC or pulsed offset voltage. This attempt, however, increases circuit complexity and decreases performance. Additional circuitry raises power requirements. Further, the added circuitry often significantly reduces the frequency response range of the device. Still further, additional circuitry may create timing hazards, that is, functional timing requirements which if not met, produce device lock up or erroneous results. Finally, moving the dead zone does not reduce the problem, it merely shifts it to a less common operating area for a PLL.
It is therefore an object of the present invention to provide a method and apparatus for detecting a difference in phase between two signals with reduced propagation delay.
It is further object of the present invention to provide such a method and apparatus for providing a linear response curve when the phase difference lies in the vicinity of 180.degree..
It is further object of the present invention to provide such a method and apparatus for reducing the number of components in a phase detector.
It is further object of the present invention to provide such a method and apparatus for reducing the power consumption in a phase detector.
It is further object of the present invention to provide such a method and apparatus for providing a TTL-compatible phase detector.
It is further object of the present invention to provide such a method and apparatus for providing a CMOS-compatible phase detector.
Still other objects and advantages of the present invention will become apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.